the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos field effect transistor pa2450b n-channel mos field effect transistor for switching data sheet document no. g16635ej1v0ds00 (1st edition) date published january 2004 ns cp(k) printed in japan 2004 description the pa2450b is a switching device, which can be driven directly by a 2.5 v power source. the pa2450b features a low on-state resistance and excellent switching characteristics, and is suitable for applications such as power sw itch of portable machine and so on. features ? 2.5 v drive available ? low on-state resistance r ds(on)1 = 17.5 m ? max. (v gs = 4.5 v, i d = 4.0 a) r ds(on)2 = 18.5 m ? max. (v gs = 4.0 v, i d = 4.0 a) r ds(on)3 = 22.0 m ? max. (v gs = 3.1 v, i d = 4.0 a) r ds(on)4 = 27.5 m ? max. (v gs = 2.5 v, i d = 4.0 a) ? built-in g-s protection diode against esd ordering information part number package pa2450btl 6pin hwson (4521) absolute maximum ratings (t a = 25c) drain to source voltage (v gs = 0 v) v dss 20.0 v gate to source voltage (v ds = 0 v) v gss 12.0 v drain current (dc) note1 i d(dc) 8.6 a drain current (pulse) note2 i d(pulse) 80.0 a total power dissipation (2 units) note1 p t1 2.5 w total power dissipation (2 units) note3 p t2 0.7 w channel temperature t ch 150 c storage temperature t stg ? 55 to +150 c notes 1. mounted on ceramic board of 50 cm 2 x 1.1 mm 2. pw 10 s, duty cycle 1% 3. mounted on fr-4 board of 50 cm 2 x 1.1 mm remark the diode connected between the gate and source of the transistor serves as a protector against esd. when this device actually used, an additional protection ci rcuit is externally required if a voltage exceeding the rated voltage may be applied to this device. package drawing (unit: mm) 1 2 3 6 5 4 4.40.1 5.00.1 0.50.1 0.50.1 0.25 +0.1 -0.05 0.1450.05 0.8 max. 0.05 +0 -0.05 7 (0.9) (0.15) (1.45) (2.2) (0.5) 1.850.1 2.00.1 1,2: 3: 7: each lead has same dimensions. source 1 gate 1 drain 5,6: 4: source 2 gate 2 equivalent circuit source2 body diode gate protection diode gate2 drain2 source1 body diode gate protection diode gate1 drain1
data sheet g16635ej1v0ds 2 characteristics symbol test conditions min. typ. max. unit zero gate voltage drain current i dss v ds = 20.0 v, v gs = 0 v 1.0 a gate leakage current i gss v gs = 12.0 v, v ds = 0 v 10.0 a gate cut-off voltage v gs(off) v ds = 10.0 v, i d = 1.0 ma 0.50 1.50 v forward transfer admittance note | y fs | v ds = 10.0 v, i d = 4.0 a 3.5 s drain to source on-state resistance note r ds(on)1 v gs = 4.5 v, i d = 4.0 a 11.0 12.5 17.5 m ? r ds(on)2 v gs = 4.0 v, i d = 4.0 a 11.5 13.0 18.5 m ? r ds(on)3 v gs = 3.1 v, i d = 4.0 a 12.0 14.5 22.0 m ? r ds(on)4 v gs = 2.5 v, i d = 4.0 a 15.3 18.0 27.5 m ? input capacitance c iss v ds = 10.0 v 520 pf output capacitance c oss v gs = 0 v 133 pf reverse transfer capacitance c rss f = 1.0 mhz 92 pf turn-on delay time t d(on) v dd = 10.0 v 21 ns rise time t r i d = 4.0 a 86 ns turn-off delay time t d(off) v gs = 4.0 v 124 ns fall time t f r g = 6 ? 107 ns total gate charge q g v dd = 16.0 v 8.0 nc gate to source charge q gs v gs = 4.0 v 1.3 nc gate to drain charge q gd i d = 8.6 a 3.3 nc body diode forward voltage note v f(s-d) i f = 8.6 a, v gs = 0 v 0.83 v reverse recovery time t rr i f = 8.6 a, v gs = 0 v 128 ns reverse recovery charge q rr di/dt = 100 a/ s 129 nc note pulsed: pw 350 s, duty cycle 2% test circuit 2 gate charge test circuit 1 switching time pg. r g 0 v gs d.u.t. r l v dd = 1 s duty cycle 1% pg. 50 ? d.u.t. r l v dd i g = 2 ma v gs wave form v ds wave form v gs v ds 10% 0 0 90% 90% 90% v gs v ds t on t off t d(on) t r t d(off) t f 10% 10%
data sheet g16635ej1v0ds 3 derating factor of forward bias safe operating area total power dissipation vs. ambient temperature dt - percentage of rated power - % 0 20 40 60 80 100 120 0 25 50 75 100 125 150 175 t a - ambient temperature - c p t - total power dissipation - w 0 0.5 1 1.5 2 2.5 3 0 25 50 75 100 125 150 175 mounted on ceramic board of 50 cm 2 x 1.1 mm, 2 units mounted on fr-4 board of 50 cm 2 x 1.1 mm, 2 units t a - ambient temperature - c forward bias safe operating area i d - drain current - a 0.01 0.1 1 10 100 1000 0.1 1 10 100 r ds(on) limited (at v gs = 4.5 v) single pulse mounted on ceramic board o f 50 cm 2 x 1.1 mm p d (fet1) : p d (fet2) = 1:1 pw = 10 s i d(pulse) i d(dc) dc (2 units) 100 s 30 ms 1 ms 10 ms v ds - drain to source voltage - v transient thermal resistance vs. pulse width r th(ch-a) - transient thermal resistance - c/w 0.1 1 10 100 1000 mounted on ceramic board o f 50 cm 2 x 1.1 mm single pulse p d (fet1) : p d (fet2) = 1:1 mounted on fr-4 board o f 50 cm 2 x 1.1 mm pw - pulse width - s 1 m 10 m 100 m 1 10 100 1000
data sheet g16635ej1v0ds 4 drain current vs. drain to source voltage forward transfer characteristics i d - drain current - a 0 10 20 30 40 50 0 0.2 0.4 0.6 0.8 1 1.2 pulsed v gs = 4.5 v 4.0 v 3.1 v 2.5 v v ds - drain to source voltage - v i d - drain current - a 0.001 0.01 0.1 1 10 100 00.511.522.53 v ds = 10.0 v pulsed t a = 125c 75c 25c ? 25c v gs - gate to source voltage - v gate cut-off voltage vs. channel temperature forward transfer admittance vs. drain current v gs(off) - gate cut-off voltage - v 0.4 0.6 0.8 1 1.2 1.4 -50 0 50 100 150 v ds = 10.0 v i d = 1.0 ma t ch - channel temperature - c | y fs | - forward transfer admittance - s 0.01 0.1 1 10 0.01 0.1 1 10 v ds = 10.0 v pulsed t a = ? 25c 25c 75c 125c i d - drain current - a drain to source on-state resistance vs. drain current drain to source on-state resistance vs. gate to source voltage r ds(on) - drain to source on-state resistance - m ? ? 0 10 20 30 40 024681012 i d = 4.0 a pulsed v gs - gate to source voltage - v
data sheet g16635ej1v0ds 5 drain to source on-state resistance vs. channel temperature capacitance vs. drain to source voltage r ds(on) - drain to source on-state resistance - m ? ? i d - drain current - a v gs - gate to drain voltage - v 0 1 2 3 4 02468 i d = 8.6 a v dd = 4.0 v 10.0 v 16.0 v q g - gate charge - nc source to drain diode forward voltage i f - diode forward current - a 0.01 0.1 1 10 100 0.4 0.6 0.8 1 1.2 v gs = 0 v pulsed v f(s-d) - source to drain voltage - v
data sheet g16635ej1v0ds 6 when you use this device, in order to prevent a customer?s hazard and damage, use it with understanding the following contents. if used exceed ing recommended conditio ns, there is a possibility of causing failure of the device and characteristic degradation. 1. when you mount the device on a subs trate, carry out within our recommended soldering conditions of infrared reflow. if mounted exceeding the conditions, the characteri stic of a device may be degraded and it may result in failure. 2. when you wash the device mounted the substrate, carry out within our recommended conditions. if washed exceeding the conditions, the characteristic of a dev ice may be degraded and it may result in failure. 3. when you use ultrasonic wave to substrate after the dev ice mounting, prevent from to uching a resonance generator directly. if it touches, the characteristic of a devi ce may be degraded and it may result in failure. 4. please refer to figure 1 as an example of the land pattern. optimize the land pattern in consideration of density, appearance of solder fillets, common difference, etc in an actual design. figure 1. example of the land pattern 3.86 2.04 0.83 0.30 unit: mm 0.50 1.16
data sheet g16635ej1v0ds 7 5. this device is very thin device and should be handled with caution for mechanical stress. the rate of distortion applied to the device should become below 2000 . note1 if the rate of distortion exceeds 2000 , the characteristic of a device may be degraded and it may result in failure. figure 2. direction of substrate and stress the substrate that mounted the device is on a stand with a support width of 24 mm. the device is turned downward. the stress is applied from a top. measurement position stress support width 24 mm substrate: 33 x 6 mm, t = 0.5 mm, fr-4 the direction of a device: device bend figure 3. example of the bend and the rate of distortion note2 0 0 0.2 0.4 0.6 0.8 1 1000 2000 3000 4000 5000 6000 bend - mm the rate of distortion - recommended condition note 1. definition of rate of distortion(written as in this document) = (l ? l 0 )/l 0 l 0 : distance for two arbitrary points before receiving stress. l: distance above-mentione d when receiving stress. 2. the relation of the distortion and the bend changes with several conditions, such as a size of substrate and so on.
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